The present invention relates to a phase-locked loop apparatus and, more particularly, to a phase-locked loop apparatus improved by digitizing a phase-locked loop which is used to reproduce a clock for reproducing digital data recorded on recording media such as optical disk media, magneto-optical disk media, and magnetic media.
Optical disk apparatuses are widely known as one of apparatuses for recording and reproducing digital data. In the optical disk apparatus, a phase-locked loop (PLL) circuit is conventionally used to lock a phase of a clock component included in a reproduction signal and a phase of a reproduction clock, when the digital data is reproduced. Particularly, an erasable optical disk medium has plural unit blocks called xe2x80x9csectorsxe2x80x9d, each of which comprises a set of a header part on which address information and the like is written and a data part on which the digital data is actually recorded. The phase locking is performed sector by sector by the phase-locked loop.
In order to perform this intermittent reproduction normally, the header part and data part have locking patterns (VFO patterns) 42a-42d, as shown in FIG. 19, each of which comprises a single pattern (single frequency). The data reproduction is performed using a method of increasing the response characteristic of the phase-locked loop circuit to perform high-speed and stable phase locking in these VFO pattern areas, and decreasing the response characteristic of the phase-locked loop circuit before ends of the VFO pattern areas to reduce influences of noises and the like, thereby to maintain a locked state.
FIG. 19 is a diagram showing a data format in a sector of an optical disk reproduction apparatus. In the figure, reference numeral 43 designates a sector mark (hereinafter referred to as SM) indicating a start position of the sector. Numeral 44 designates an address mark (hereinafter referred to as AM) indicating a start position of address information. Numeral 45 designates address information (hereinafter referred to as ID) indicating the address of the sector. Numeral 46 designates a postamble (hereinafter referred to as PA) indicating an end point of each of the header part and the data part. Numeral 47 designates a data mark (hereinafter referred to as DM) indicating a start position of data 48.
FIG. 20 is a block diagram illustrating a digital data reproduction circuit of a prior art optical disk reproduction apparatus.
The prior art optical disk reproduction apparatus as shown in FIG. 20 is constituted by an optical disk 49, a reproduction means 50, a waveform equalization means 1, a binarization means 51, a phase-locked loop circuit 52, a loop gain switching unit 57, and a demodulation circuit 58. The phase-locked loop circuit 52 is constituted by a phase comparator 53, a loop filter 54, an amplifier 55, and a Voltage Controlled Oscillator (VCO) 56.
Hereinafter, its operation will be described.
On the optical disk 49 medium, digital data comprising 0 and 1, the number of continuous 0 or 1 being controlled to from 3 to 14 inclusive, is recorded as in the 8-16 modulation method for example. In a reproduction signal which is obtained by reproducing data with the reproduction means 50, as the recording density of the data in the linear direction is increased, the amplitude of a waveform having high-band frequency components is attenuated by interference. Then, the waveform equalization means 1 corrects the reproduction signal so as to emphasize its high-band frequency components. The binarization means 51 binarizes the reproduction signal having the emphasized high-band frequency components at a prescribed slice level to convert the signal into a binarized digital signal. In the phase-locked loop circuit 52, a phase of a reproduction clock as a free running frequency of the phase-locked loop circuit 52 and a phase of a clock component of the binarized signal are compared by the phase comparator 53, and the phase of the reproduction clock is changed on the basis of phase error information which is output as a result of the comparison so as to have the minimum phase error, by using the loop filter 54, the amplifier 55 and the VCO 56, whereby the phase of the clock component of the binarized signal and the phase of the reproduction clock are locked. The response characteristic of the phase-locked loop circuit 52 is switched by the loop gain switching unit 57. Then, the binarized signal and the locked reproduction clock are input to the demodulation circuit 58 to demodulate the digital data.
In the VFO pattern areas on the recording medium, a range where the reproduction is normally performed is sometimes limited due to defects of the recording medium, servo processing or signal processing in the reproduction of the recording medium. Accordingly, improvements are made to perform the phase locking surely as in a method of detecting the defects or the method as shown in FIG. 19 of detecting SM 43, AM 44, and DM 47 to make the best use of all the VFO pattern areas.
The above-mentioned prior art is adapted to a method which binarizes the reproduction signal to demodulate the digital data. However, when a signal-to-noise ratio of the reproduction signal is significantly deteriorated as the density in,the linear direction is increased, the quality of reproduced data is deteriorated.
Accordingly, as the recording density in the linear direction becomes higher, a PRML (Partial Response Maximum Likelihood) signal processing method as a signal processing method which is suitable for the high-density recording and reproduction in the linear direction is increasingly adopted. The PRML signal processing method is the one which urges intentional waveform interference for the reproduction signal, equalizes the reproduction signal with a band which is controlled to reduce emphasis on noises to the utmost, and thereafter demodulates data by a maximum likelihood decoder for demodulating the most likelihood series in accordance with a known regulation of interference. However, when this PRML signal processing method is utilized, multi-bit data obtained by sampling a reproduction clock which is locked to a phase of a clock component included in the reproduction signal should be generated.
This prior art phase-locked loop circuit is constituted by analog elements. Accordingly, a system where analog circuits and digital circuits are mixed in a complex manner is obtained and this system is not suitable for the integration. In addition, the dispersion of characteristics caused by the analog elements constituting the analog circuits or secular changes occur in the analog circuits. Accordingly, careful consideration should be given also to the quality control, compensation circuits and the like, whereby the cost of the digital data reproduction apparatus which is constituted by using the phase-locked loop circuit is increased.
Therefore, a system which is suitable for the PRML signal processing should be realized by digitizing also a clock reproduction circuit and equalization means, thereby increasing the quality of reproduced data and reducing the cost by the integration also in the high-density recording and reproduction.
However, when the phase-locked loop circuit for performing the clock reproduction is realized by digital circuits, as a transfer rate is increased, a delay amount of the phase-locked loop is increased and a capture range indicating a range where a frequency and a phase can be locked at the phase locking is reduced. When phase error information is obtained from analog signals, an amount of a continuous time error can be handled. However, when the phase error information is obtained from digital data after the sampling, the phase error information should be assumed from an amplitude value in the vicinity of a zero cross point. Therefore, sufficient continuous areas of phase error signals cannot be secured.
When the capture range is reduced, in a case where the frequency of the reproduction clock is significantly different from the frequency of the clock component included in the reproduction signal, the phase locking is not completed only by the VFO pattern areas. Therefore, errors such as burst errors are increased at the reproduction time and thereby the data quality is deteriorated.
In addition, the VFO pattern areas are small and, in the case of erasable disks, there is an increase in a risk that the first half part of that area is deteriorated as the number of writing times is increased or a DC offset position is substantially shifted. Therefore, when the frequency of the reproduction clock is significantly different from the frequency of the clock component included in the reproduction signal, errors such as burst errors at the reproduction time are increased and the quality of data is deteriorated.
Further, when data recorded on the recording medium does not include the VFO pattern, the reproduction signal is a random signal. Therefore, when the phase locking is performed using only the phase information, the capture range in locking the phase of the clock component of the reproduction signal and the phase of the reproduction clock is reduced. Accordingly, when both frequencies are significantly different from each other, the phase locking cannot be performed surely.
The present invention is directed to solve the above problems, and an object of the present invention is to provide a phase-locked loop apparatus: which detects phase information from a reproduction signal as well as detects frequency information from a temporal change of the phase information, has a wider capture range than that of an analog phase-locked loop circuit, and performs the phase locking at a high speed, when a phase-locked loop circuit is digitized.
In addition, an object of the present invention is to provide a phase-locked loop apparatus which predicts phase error information to obtain a wider capture range, as well as locks the phase of the reproduction clock and the phase of the clock component included in the reproduction digital signal at a high speed and with good stability, when the phase-locked loop circuit is digitized.
Further, in addition to the above objects, the present invention has another object to provide a phase-locked loop apparatus which can perform the phase locking also for digital data having no pattern signal comprising a single frequency in a data format of digital information which is recorded on a recording medium.
Furthermore, in addition to the above objects, another object of the present invention is to provide a low cost phase-locked loop apparatus which can be integrated easily and has higher reliability.
To solve the above problems, according to first aspect of the present invention, a phase locked loop apparatus which reads digital data recorded on a recording medium in a predetermined data format, and generates a reproduction clock for obtaining a reproduction digital signal, comprises: a phase error information detection means for detecting phase error information from a signal area other than a single frequency data area comprising a single frequency in the data format; a frequency error information detection means for detecting frequency error information from the single frequency data area comprising the single frequency in the data format; and a feedback loop for locking a phase of the reproduction clock and a phase of a clock component included in the reproduction digital signal, on the basis of the phase error information and the frequency error information, whereby a phase-locked loop circuit is digitized.
According to the present invention, clock reproduction which is suitable for a PRML signal processing method can be performed. In addition, when a multi-bit digital signal which is obtained by the sampling by the A/D converter is a VFO pattern signal, a phase error signal and a frequency error signal are input to the feedback loop as input signals. Therefore, in a VFO pattern area, even when a reproduction signal includes DC components, the phase error is detected correctly, whereby the VFO pattern area can be effectively utilized. Further, a frequency error detector detects a correct inclination of a phase error curve. Therefore, a capture range is substantially extended, whereby a phase-locked loop apparatus which can perform the phase locking at a high speed and with good stability even when a frequency of a reproduction clock is significantly different from a frequency of a clock component included in the reproduction signal can be provided.
According to a second aspect of the present invention, a phase-locked loop apparatus which reads digital data recorded on a recording medium in a predetermined data format, and generates a reproduction clock for obtaining a reproduction digital signal, comprises: a waveform equalization means for emphasizing a predetermined frequency band of a reproduction signal; an A/D conversion means for sampling the reproduction signal, the predetermined frequency band of which is emphasized by the waveform equalization means, using a reproduction clock at a time when a digital signal is reproduced, to obtain a digital signal; a high-pass filter (HPF) means for removing DC components from the digital signal obtained by the sampling when the obtained digital signal is a VFO pattern signal; a low-band component suppression means for suppressing low-band noises of the digital signal obtained by the sampling when the obtained digital signal is a signal other than the VFO pattern signal; a zero cross detection means for detecting a position where an output of the HPF means or low-band component suppression means crosses a zero level, and outputting a zero cross flag; a phase error detection means for detecting a phase error from data in the vicinity of a zero cross, using the zero cross flag and the output of the HPF means or low-band component suppression means; xe2x80x9cnxe2x80x9d pieces of a holding means for holding continuous xe2x80x9cnxe2x80x9d (xe2x80x9cnxe2x80x9d is a positive integer) pieces of the phase errors on the basis of the zero cross flag, which holding means are connected in series with each other; a frequency error detection means for detecting an inclination of a phase error curve from outputs of the respective xe2x80x9cnxe2x80x9d pieces of holding means, and converting the inclination into a frequency error; a phase controlling loop filter means for receiving a phase error signal which is an output of the phase error detection means and a frequency error signal which is an output of the frequency error detection means, as input signals when the digital signal obtained by the sampling is the VFO pattern signal, and receiving the phase error signal which is the output of the phase error detection means as an input signal when the obtained digital signal is a signal other than the VFO pattern signal; and an oscillator means for generating a reproduction clock on the basis of an output of the phase controlling loop filter means, whereby a phase-locked loop circuit is digitized.
According to the present invention, the clock reproduction which is suitable for the PRML signal processing method can be performed. In addition, when a multi-bit digital signal which is obtained by the sampling by the A/D converter is a VFO pattern signal, the phase error signal and the frequency error signal are input to the feedback loop as input signals. Therefore, in a VFO pattern area, even when a reproduction signal includes DC components, the phase error is detected correctly, whereby the VFO pattern area can be effectively utilized. Further, the frequency error detector detects a correct inclination of a phase error curve. Therefore, the capture range is substantially extended, whereby a phase-locked loop apparatus which can perform the phase locking at a high speed and with good stability even when a frequency of the reproduction clock is significantly different from a frequency of a clock component included in the reproduction signal can be provided.
According to a third aspect of the present invention, a phase-locked loop apparatus which reads digital data recorded on a recording medium in a predetermined data format, and generates a reproduction clock for obtaining a reproduction digital signal, comprises: a phase error information detection means for detecting phase error information from a random signal area in the digital data; a frequency error information detection means for detecting frequency error information from the random signal area in the digital data; and a feedback loop for locking a phase of the reproduction clock and a phase of a clock component included in the reproduction digital signal on the basis of the phase error information and the frequency error information, and a feedback loop phase controlling loop filter receives a phase error signal and a frequency error signal as input signals.
According to the present invention, when re-locking of phases is required in an area of data other than the VFO pattern because of defects of a recording medium or the like, the capture range is extended as well as the re-locking time is reduced. Therefore, deterioration in the quality of reproduced data due to burst errors or the like can be minimized. Further, a phase-locked loop apparatus which can obtain the same effects as described above also in a recording medium having no VFO pattern area can be provided.
According to a fourth aspect of the present invention, a phase-locked loop apparatus which reads digital data recorded on a recording medium in a predetermined data format, and generates a reproduction clock for obtaining a reproduction digital signal, comprises: a waveform equalization means for emphasizing a predetermined frequency band of a reproduction signal; an A/D conversion means for sampling the reproduction signal, the predetermined frequency band of which is emphasized by the waveform equalization means, using a reproduction clock at a time when a digital signal is reproduced, to obtain a digital signal; a low-band component suppression means for suppressing low-band noises of the digital signal obtained by the sampling; a zero cross detection means for detecting a position where an output of the low-band component suppression means crosses a zero level, and outputting a zero cross flag; a phase error detection means for detecting a phase error from data in the vicinity of a zero cross, using the zero cross flag and the output of the low-band component suppression means; xe2x80x9cnxe2x80x9d pieces of a holding means for holding continuous xe2x80x9cnxe2x80x9d (xe2x80x9cnxe2x80x9d is a positive integer) pieces of the phase errors on the basis of the zero cross flag, which holding means are connected in series with each other; a frequency error detection means for detecting an inclination of a phase error curve from outputs of the respective xe2x80x9cnxe2x80x9d pieces of holding means, and converting the inclination into a frequency error; a phase controlling loop filter means for receiving a phase error signal which is an output of the phase error detection means and a frequency error signal which is an output of the frequency error detection means, as input signals; and an oscillator means for generating a reproduction clock on the basis of an output of the phase controlling loop filter means, and the phase controlling loop filter receives the phase error signal and the frequency signal as input signals.
According to the present invention, when the re-locking of phases is required in an area of data other than the VFO pattern because of defects of a recording medium or the like, the capture range is extended as well as the re-locking time is reduced. Therefore, deterioration in the quality of reproduced data due to burst errors or the like can be minimized. Further, a phase-locked loop apparatus which can obtain the same effects as described above also in a recording medium having no VFO pattern area can be provided.
According to a fifth aspect of the present invention, in the phase-locked loop apparatus of the second or fourth aspect, the phase error detection means comprises: a first holding means and a second holding means for holding amplitudes of reproduction signals at adjacent zero cross positions for each zero cross, on the basis of the zero cross flag; a subtraction means for receiving an output of the first holding means and an output of the second holding means as inputs; a polarity decision means for deciding whether a reproduction waveform at a timing when the amplitude is held by the first holding means is a leading edge or a trailing edge, on the basis of previous and subsequent data; and a sign manipulation means for manipulating a sign of an output of the subtraction means on the basis of an output of the polarity decision means.
According to the present invention, correlation of phase error information in the temporal direction is enhanced, whereby the phase error detection having resistance to high-band noise components can be performed. Therefore, a phase-locked loop apparatus which can perform the phase locking without being affected by the high-band noises as well as can maintain a locked state stably can be provided.
According to a sixth aspect of the present invention, in the phase-locked loop apparatus of the second or fourth aspect, the frequency error detection means comprises: a plural subtraction means each obtaining a difference between the phase errors output by predetermined two holding means among the xe2x80x9cnxe2x80x9d pieces of holding means; a polarity decision means for deciding which is a polarity of an output of each of the plural subtraction means among positive, negative, and zero; a selection means for removing information at a discontinuous point of the phase error curve on the basis of plural inclination information output by the plural subtraction means, and selecting information of an inclination where frequency information is obtained stably; a balancing means for balancing the inclination information selected by the selection means; and a gain stage for arbitrarily adjusting a gain of an output of the balancing means, and outputting the adjusted gain to the phase controlling loop filter means, and a correct frequency error is assumed using only a phase error in a linear and continuous area of the phase error curve.
According to the present invention, the capture range is extended as well as the response speed of frequency control is increased. Therefore, a phase-locked loop apparatus which can perform the phase locking at a high speed can be provided.
According to a seventh aspect of the present invention, in the phase-locked loop apparatus of the second or fourth aspects, the frequency error detection means of the sixth aspect is included and the phase controlling loop filter means comprises: a phase error absolute value conversion means for converting the output of the phase error detection means into an absolute value; a phase decision means for deciding a magnitude of the obtained absolute value with a predetermined threshold; a start time setting means for manipulating a control start time so as to start an operation of a loop filter from the vicinity of a zero phase as a stable point of the phase error curve when control is executed using the phase error signal on the basis of an output of the selection means of the frequency error detection means of the sixth aspect and an output of the phase decision means; and loop filter means for outputting a control signal for the oscillator means on the basis of an output of the start time setting means.
According to the present invention, when the frequency error detection means of the sixth aspect is utilized, a time for performing the phase locking is made equal to a case where a zero phase start is performing, i.e., the phase of the reproduction clock is adjusted so that the clock component included in the reproduction signal and the reproduction clock are in phase and then the phase locking is started. Therefore, a phase-locked loop apparatus which can perform the phase locking at the minimum time can be provided.
According to an eighth aspect of the present invention, in the phase-locked loop apparatus of the second or fourth aspect, the phase controlling loop filter means comprises: a frequency error absolute value conversion means for converting the output of the frequency error detection means into an absolute value; a frequency decision means for deciding a magnitude of the obtained absolute value with a predetermined threshold; an error selection means for performing switching on the basis of an output of the frequency decision means, so that control is executed using only the phase error signal when a frequency of the reproduction clock is within a phase locked range, and using only the frequency error signal when the frequency of the reproduction clock is outside the phase locked range; and a loop filter means for outputting a control signal for the oscillator means on the basis of an output of the error selection means.
According to the present invention, when the frequency of the reproduction clock is quite different from the frequency of the clock component included in the reproduction signal and is outside the phase locked range, the control is executed using only the frequency error signal. Therefore, relative to a case where the phase error is simultaneously fed back, the frequency locking is completed at a higher speed. On the other hand, when the frequency of the reproduction clock is within the phase locked range, the control is executed using only the phase error signal. Therefore, the phase locking is completed smoothly. Accordingly, a phase-locked loop apparatus which can execute the optimal control making the best use of respective advantages of the phase error and frequency error can be provided.
According to a ninth aspect of the present invention, a phase-locked loop apparatus which reads digital data recorded on a recording medium in a predetermined data format, and generates a reproduction clock for obtaining a reproduction digital signal, comprises: an acquisition phase error information detection means for detecting acquisition phase error information from a single frequency data area comprising a single frequency in the data format; a tracking phase error information detection means for detecting tracking phase error information from a random signal data area comprising a random signal in the digital data; and a feedback loop for locking a phase of the reproduction clock and a phase of a clock component included in the reproduction digital signal on the basis of the acquisition phase error information and the tracking phase error information.
In the present invention, in the pattern area comprising the single frequency, a correct phase error can be detected also when the reproduction signal includes DC components. Therefore, the pattern area can be utilized effectively as well as a continuous area of the phase error curve can be expanded, whereby the capture range is substantially extended. Accordingly, a phase-locked loop apparatus which can lock the phase of the reproduction clock and the phase of the clock component included in the reproduction digital data at a high speed and with good stability also when the frequency of the reproduction clock is significantly different from the frequency of the clock component included in the reproduction signal can be provided.
According to a tenth aspect of the present invention, a phase-locked loop apparatus which reads digital data recorded on a recording medium in a predetermined data format, and generates a reproduction clock for obtaining a reproduction digital signal, comprises: an A/D conversion means for sampling digital data in the data format with a reproduction clock, to obtain a digital data signal; a band-pass filter means for removing direct current components from the digital data signal obtained by the sampling, during reproduction of a single frequency data area in the data format; a zero cross detection means for detecting positions where an output signal of the band-pass filter and the digital data signal cross a zero level, and outputting respective zero cross flags; a cycle counter means for starting counting with the zero cross flag as a start point; an acquisition phase error detection means for detecting a phase error from the output signal of the band-pass filter at a timing when a timing signal is obtained by the cycle counter means, a tracking phase error detection means for detecting a phase error of the digital data signal on the basis of the zero cross flag; a loop filter means for receiving a phase error signal which is an output of the acquisition phase error detection means as an input signal when the digital signal obtained by the sampling is a VFO pattern signal, and receiving a phase error signal which is an output of the tracking phase error detection means as an input signal when the obtained digital signal is a signal other than the VFO pattern signal; a D/A conversion means for converting an output signal of the loop filter means into an analog signal; and an oscillator means for generating the reproduction clock on the basis of the analog signal output by the D/A conversion means.
In the present invention, a correct phase error can be detected in the pattern area comprising the single frequency also when the reproduction signal includes DC components. Therefore, the pattern area can be utilized effectively as well as the continuous area of the phase error curve can be expanded, whereby the capture range is substantially extended. Therefore, also when the frequency of the reproduction clock is significantly different from the frequency of the clock component included in the reproduction signal, the phase of the reproduction clock and the phase of the clock component included in the reproduction digital data can be locked at a high speed and with good stability. Further, when the phase-locked loop is digitized, the integration can be easily performed when it is realized as an IC, whereby the cost can be reduced as well as the clock reproduction which is suitable for the PRML signal processing method can be performed. Therefore, a system which is suitable for the high-density recording/reproduction can be provided.
According to an eleventh aspect of the present invention, a phase-locked loop apparatus which reads digital data recorded on a recording medium in a predetermined data format, and generates a reproduction clock for obtaining a reproduction digital signal, comprises: a first phase error information detection means for obtaining first phase error information from prediction of a zero cross position in a random signal area in the digital data; a second phase error information detection means for detecting second phase error information from a random signal in the digital data; and a feedback loop for locking a phase of the reproduction clock and a phase of a clock component included in the reproduction digital signal on the basis of the first phase error information and the second phase error information.
In the present invention, the continuous area of the phase error curve can be expanded also for digital data having no single frequency signal in data format, the capture range is substantially extended. Therefore, a phase-locked loop apparatus can be provided which can lock the phase of the reproduction clock and the phase of the clock component included in the reproduction digital data at a high speed and with good stability, as well as can reduce the re-locking time when the re-locking of phases is required because of defects of a recording medium or the like, whereby the deterioration in the quality of reproduced data due to burst errors or the like can be minimized.
According to a twelfth aspect of the present invention, a phase-locked loop apparatus which reads digital data recorded on a recording medium in a predetermined data format, and generates a reproduction clock for obtaining a reproduction digital signal, comprises: a loop gain control means for outputting a loop gain control signal for increasing a phase-locking capacity for a predetermined period from a phase-locking start; an A/D conversion means for sampling the digital data with a reproduction clock, to obtain a digital data signal; a zero cross position prediction means for predicting a zero cross position of random data in the digital data signal obtained by the sampling; an acquisition phase error detection means for detecting phase error information of the random data, from an output signal of the zero cross position prediction means and the digital data signal; a zero cross detection means for detecting a position where the obtained digital data signal crosses a zero level, and outputting a zero cross flag; a tracking phase error detection means for detecting a phase error of the digital data signal on the basis of the zero cross flag; a loop filter means for receiving a phase error signal which is an output of the acquisition phase error detection means as an input signal, and receiving a phase error signal which is an output of the tracking phase error detection means as an input signal; a D/A conversion means for converting an output signal of the loop filter into an analog signal; and an oscillator means for generating the reproduction clock on the basis of the analog signal output by the D/A conversion means.
According to the present invention, when the zero cross position prediction means is utilized, the continuous area of the phase error curve is expanded also for digital data having no single frequency signal in a data format, whereby the capture range is extended. Therefore, the phase of the reproduction clock and the phase of the clock component included in the reproduction digital data can be locked at a high speed and with good stability, as well as the re-locking time can be reduced when the re-locking of phases is required because of defects of a recording medium or the like, whereby the deterioration in the quality of reproduced data due to burst errors or the like can be minimized. Further, when the phase-locked loop is digitized, the integration can be performed easier when it is realized as an IC. Therefore, the cost can be reduced as well as the clock reproduction which is suitable for the PRML signal processing method can be performed, whereby a system which is suitable for high-density recording/reproduction can be provided.